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| LH52258A FEATURES * Fast Access Times: 20/25 ns * Low-Power Standby when Deselected * TTL Compatible I/O * 5 V 10% Supply * Fully-Static Operation * JEDEC Standard Pinout * Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION The LH52258A is a high-speed 262,144 bit static RAM organized as 32K x 8. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. This RAM is fully static in operation. The Chip Enable (E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH). Standby power (ISB1) drops to its lowest level if E is raised to within 0.2 V of VCC. Write cycles occur when both Chip Enable (E) and Write Enable (W) are LOW. Data is transferred from the DQ pins to the memory location specified by the 15 address lines. The proper use of the Output Enable control (G) can prevent bus contention. CMOS 32K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address. High-frequency design techniques should be employed to obtain the best performance from this device. Solid, low-impedance power and ground planes, with high-frequency decoupling capacitors, are recommended. Series termination of the inputs should be considered when transmission line effects occur. PIN CONNECTIONS 28-PIN DIP 28-PIN SOJ A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 52258A-1D TOP VIEW Figure 1. Pin Connections for DIP and SOJ Packages 1 LH52258A CMOS 32K x 8 Static RAM A4 A1 A2 A6 A7 A12 A14 ROW DECODER A5 MEMORY ARRAY (32,768 x 8) DQ0 - DQ7 8 BLOCK DECODE A0 A3 I/O CIRCUIT COLUMN DECODE A10 A11 A9 A8 A13 8 8 E W G 52258A-2 Figure 2. LH52258A Block Diagram TRUTH TABLE E G W MODE DQ ICC PIN DESCRIPTIONS PIN DESCRIPTION H L L L X H L X X H H L Not Selected Selected Read Write High-Z High-Z Data Out Data In Standby Active Active Active A0 - A14 DQ0 - DQ7 E G W VCC VSS Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Positive Power Supply Ground 2 CMOS 32K x 8 Static RAM LH52258A ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING VCC to VSS Potential Input Voltage Range DC Output Current 2 -0.5 V to 7 V -0.5 V to VCC + 0.5 V 40 mA -65o to 150oC 1.0 W Storage Temperature Range Power Dissipation (Package Limit) NOTES: 1. Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the `Operating Range' section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGES SYMBOL PARAMETER MIN TYP MAX UNIT oC TA VCC VSS VIL VIH Temperature, Ambient Supply Voltage Supply Voltage Logic `0' Input Voltage Logic `1' Input Voltage 1 0 4.5 0 -0.5 2.2 5.0 0 70 5.5 0 0.8 VCC + 0.5 V V V V NOTE: 1. Negative undershoot of up to 3.0 V is permitted once per cycle. DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT ICC1 Operating Current 2 tRC = 20 ns G VIH, E VIL, IOUT = 0 mA, tCYCLE = 20 ns tRC = 25 ns G VIH, E VIL, IOUT = 0 mA, tCYCLE = 25 ns E VCC - 0.2 V E VIH VCC = 5.5 V, VIN = 0 V to VCC VCC = 5.5 V, VIN = 0 V to VCC IOH = -4.0 mA IOL = 8.0 m A E VCC - 0.2 V VCC = 3 V, E VCC - 0.2 V 2 -2 -2 2.4 95 150 mA ICC1 ISB1 ISB2 ILI ILO VOH VOL VDR IDR Operating Current 2 Standby Current Standby Current Input Leakage Current I/O Leakage Current Output High Voltage Output Low Voltage Data Retention Voltage Data Retention Current 90 0.005 6 140 1 15 2 2 mA mA mA A A V V V A 0.4 5.5 250 NOTES: 1. Typical values at VCC = 5 V, TA = 25C. 2. ICC is dependent upon output loading and cycle rates. Specified values are with outputs open, operating at specified cycle times. 3 LH52258A CMOS 32K x 8 Static RAM AC TEST CONDITIONS PARAMETER RATING +5 V Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels Output Load, Timing Tests V SS to 3 V 3 ns 1.5 V Figure 3 255 30 pF * DQ PINS 480 CAPACITANCE 1,2 RATING PARAMETER CIN (Input Capacitance) CDQ (I/O Capacitance) 7 pF 8 pF * INCLUDES JIG AND SCOPE CAPACITANCES 52258A-3 NOTES: 1. Capacitances are maximum values at 25oC measured at 1.0 MHz with VBias = 0 V and VCC = 5.0 V. 2. Guaranteed but not tested. Figure 3. Output Load Circuit DATA RETENTION TIMING E must be held above the lesser of VIH or VCC - 0.2 V to prevent improper operation when VCC < 4.5 V. E must be VCC - 0.2 V or greater to meet IDR specification. All other inputs are `Don't Care.' 0 ns tRC MIN VCC 4.5 V VIH VDR VIL E E VDR - 0.2 V 52258A-4 Figure 4. Data Retention Timing 4 CMOS 32K x 8 Static RAM LH52258A AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL DESCRIPTION MIN -2 0 MAX MIN -25 MAX UNITS READ CYCLE tRC tAA tOH tEA tELZ tEHZ tGA tGLZ tGHZ tPU tPD Read Cycle Time Address Access Time Output Hold from Address Change E Low to Valid Data E Low to Output Active 2,3 E High to Output High-Z G Low to Valid Data G Low to Output Active 2,3 G High to Output High-Z 2,3 2,3 20 20 4 20 4 0 10 10 0 0 0 3 25 25 4 25 4 0 12 12 0 9 0 0 25 30 10 ns ns ns ns ns ns ns ns ns ns ns E Low to Power Up Time 3 E High to Power Down Time WRITE CYCLE tWC tEW tAW tAS tAH tWP tDW tDH tWHZ tWLZ Write Cycle Time E Low to End of Write Address Valid to End of Write Address Setup Address Hold from End of Write W Pulse Width Input Data Setup Time Input Data Hold Time W Low to Output High-Z 2,3 W High to Output Active 2,3 20 15 15 0 0 12 10 0 8 0 25 20 20 0 0 15 12 0 10 0 ns ns ns ns ns ns ns ns ns ns NOTES: 1. AC Electrical Characteristics specified at `AC Test Conditions' levels. 2. Active output to High-Z and High-Z to output active tests specified for a 500 mV transition from steady state levels into the test load. The test load has 5 pF capacitances. 3. Guaranteed by design but not tested. 5 LH52258A CMOS 32K x 8 Static RAM Read Cycle No. 2 Chip is in Read Mode: W is HIGH. Timing illustrated for the case when addresses are valid before E goes LOW. Data Out is not specified to be valid until tEA or tGA, but may become valid as soon as tELZ or tGLZ. Outputs will transition from High-Z to Valid Data Out. Valid data will be present following tGA only if tEA timing is met. TIMING DIAGRAMS - READ CYCLE Read Cycle No. 1 Chip is in Read Mode: W is HIGH, E is LOW and G is LOW. Read cycle timing is referenced from when all addresses are stable until the first address transition. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid until tAA. tRC ADDRESS VALID ADDRESS tAA tOH DQ PREVIOUS DATA VALID DATA 52258A-5 Figure 5. Read Cycle No. 1 tRC E tPD tEA tEHZ G tGA tGLZ tELZ DQ tPU VALID DATA tGHZ SUPPLY CURRENT 52258A-6 Figure 6. Read Cycle No. 2 6 CMOS 32K x 8 Static RAM LH52258A Write Cycle No. 1 (W Controlled) Chip is selected: E is LOW, G is LOW. Using only W to control Write cycles may not offer the best performance since both tWHZ and tDW timing specifications must be met. Write Cycle No. 2 (E Controlled) G is LOW. DQ lines may transition to Low-Z if the falling edge of W occurs after the falling edge of E. TIMING DIAGRAMS - WRITE CYCLE Addresses must be stable during Write cycles. The outputs will remain in the High-Z state if W is LOW when E goes LOW. If G is HIGH, the outputs will remain in the High-Z state. Although these examples illustrate timing with G active, it is recommended that G be held HIGH for all Write cycles. This will prevent the LH52258A's outputs from becoming active, preventing bus contention, thereby reducing system noise. tWC ADDRESS VALID ADDRESS tAW tAS tWP tAH W tWHZ tDW tWLZ tDH DQ DATA ON DQ LINES PREVIOUS OUTPUT HIGH-Z INPUT LOW-Z 52258A-7 Figure 7. Write Cycle No. 1 tWC ADDRESS VALID ADDRESS tEW E tAS tWP tAH W tELZ tWHZ tDW tDH DQ DATA ON DQ LINES HIGH-Z LOW-Z HIGH-Z INPUT 52258A-8 Figure 8. Write Cycle No. 2 7 LH52258A CMOS 32K x 8 Static RAM PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300) 28 15 7.05 [0.278] 6.65 [0.262] 1 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 14 0.35 [0.014] 0.15 [0.006] 7.62 [0.300] TYP. 0 TO 15 DETAIL DIMENSIONS IN MM [INCHES] 28DIP-1 28-pin, 300-mil DIP 28SOJ (SOJ28-P-300) 28 15 DETAIL 7.9 [0.311] 7.5 [0.295] 8.63 [0.340] 8.23 [0.324] 3.7 [0.146] 3.3 [0.130] 2.6 [0.102] 2.2 [0.087] 1 18.7 [0.736] 18.3 [0.720] 14 0.64 [0.025] MIN 0.8 [0.031] 0.6 [0.024] 0.102 [0.004] 0.20 [0.008] 1.15 [0.045] 0.85 [0.033] 1.27 [0.050] TYP. DIMENSIONS IN MM [INCHES] 0.53 [0.021] 0.33 [0.013] MAXIMUM LIMIT MINIMUM LIMIT 7.0 [0.276] 6.6 [0.260] 28SOJ300 28-pin, 300-mil SOJ 8 CMOS 32K x 8 Static RAM LH52258A ORDERING INFORMATION LH52258A Device Type X Package - ## Speed 20 25 Access Time (ns) D 28-pin, 300-mil DIP (DIP28-P-300) K 28-pin, 300-mil SOJ (SOJ28-P-300) CMOS 32K x 8 Static RAM Example: LH52258AK-25 (CMOS 32K x 8 Static RAM, 25 ns, 28-pin, 300-mil SOJ) 52258AMD 9 |
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